Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a portion of a convention communications system. As shown, a base station system 102 operates to provide communications between a network interface 106 and an air interface, which is typically used for wireless communications. The base station system 102 generally comprises radio equipment 108 and a radio equipment controller 110, which each have a physical layer (PHY) 112 and 114 that communicate with each other over a CPRI/OBSAI link 113. As part of the protocol for a CPRI/OBSAI system, PHY 114 generally includes a timing circuit 116 that operates to calculate the “round trip” latency between the radio equipment 108 and radio equipment controller 110.
Turning to FIG. 2, an example of a conventional PHY 114 can be seen in greater detail. Within PHY 114, there is a transmit path 118 and a receive path 120 that serially communicate data to PHY 112 over link 113 and that communicate (in parallel) data to/from the network interface 106. When performing latency calculation, the stop/start counter 126 measures the elapsed time between commas (either encoded or unencoded) detected by the comma detect circuits 122 and 124. Typically, counter 126 measures the time between a comma detected from the parallel transmit data (or transmit comma) by comma detect circuit 122 and a comma detected from the parallel receive data (or receive comma) by comma detect circuit 124. The resolution of this latency measurement is a factor in evaluating the system 100.
As a result, it is desirable to have the latency measurement be as high a resolution as possible. However, for timing circuit 116, there are drawbacks. For example, the logic for the timing circuit 116 operates in a high speed clock domain (compared to the clock domain used for the transmit and receive paths 118 and 120). This high speed configuration results in significant power consumption as well as increased risk of a false comma detection when the parallel data containing a comma is presented to the high speed clock domain from the lower speed clock domains. Therefore, there is a need for a timing circuit with improved performance.
Another example of a conventional is European Patent No. EP1814341.